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Pin 8  GND: System ground. For best jitter performance,
all bypass capacitors should be connected to this pin via
For example, to find RMIN for VGA which has fMINLOCK =
short paths.
31.469 kHz,
Pin 9  PD2 FILTER: The low-pass filter cap of between
=
fMIN = 0.85(31.469 kHz) - 2 kHz 24749
0.01 µF to 1 µF for the output of phase detector 2 is con-
nected from this pin to pin 8 (GND) via a short path. A
smaller value increases the response.
Pin 10  PHASE: A DC control voltage applied to this pin
Rounding to the closest standard 1% resistor gives RMIN = sets the phase of the flyback pulse with respect to the center
21.5 k&!.
of H sync. See Figure 10 for the input schematic.
Pin 2  H/HV POLARITY: A 0.1 µF capacitor is connected
Pin 11  FVC FILTER: A 1 µF capacitor is connected from
from this pin to ground for detecting the polarity of H/HV sync
this pin to pin 8 (GND) via a short path.
at pin 3. A low logic level at pin 2 indicates active-high H/HV
Pin 12  PD1 OUT/VCO IN: Phase detector 1 has a gated
sync to pin 3, a high level indicates active-low. See Figure 4
charge pump output which requires an external low-pass fil-
for the output schematic.
ter. For best jitter performance, the filter should be grounded
Pin 3  H/HV SYNC: This input pin accepts DC-coupled H
to pin 8 (GND) via a short path. If a voltage source is applied
or composite sync of either polarity. For best noise immunity,
to this pin, the phase detector is disabled and the VCO can
a resistor of 2 k&! or less should be connected from this pin
be controlled directly.
to pin 8 (GND) via a short path. See Figure 5 for the input
Pin 13  VREF: This is the decoupling pin for the internal
schematic.
8.2V reference. It should be decoupled to pin 8 (GND) via a
Pin 4  DUTY CYCLE: A DC voltage applied to this pin sets
short path with a cap of at least 470 µF. Do not load this pin.
the duty cycle of the H DRIVE output (pin 7), with a range of
Pin 14  VCC: 12V nominal power supply pin. This pin
approximately 30% to 70%. 2V sets the duty cycle to ap-
should be decoupled to pin 8 (GND) via a short path with a
proximately 50%. See Figure 6 for the input schematic.
cap of at least 47 µF.
Pin 5  X-RAY: This pin is for monitoring CRT anode volt-
age. If the input voltage exceeds an internal threshold, H
Input/Output Schematics
DS012917-5
DS012917-4
FIGURE 5.
FIGURE 4.
5 www.national.com
Input/Output Schematics (Continued)
DS012917-6
FIGURE 6.
DS012917-9
FIGURE 9.
DS012917-7
FIGURE 7.
DS012917-10
FIGURE 10.
DS012917-8
FIGURE 8.
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=
Consider a scanning mode transition at t 0 from f1 to f2.
Application Hints
The VCO frequency as a function of time, fVCO(t), is de-
1. Phase Control for Geometry Correction: Pin 10
scribed by the equation,
(PHASE) is designed to control static phase (picture
E"
fVCO(t) f + (f - f ) (1  exp (-t /Ä)),
1 2 1
horizontal position) as well as dynamic phase for geom-
=
where Ä 40 x 103 x CFVC.
etry correction. Complete control of static and dynamic
phase can be achieved by superposing a correction The above equation can be used to predict VCO behav-
waveform (Sawtooth and/or parabola) on the DC control ior during frequency transitions, but in practice the value
voltage at pin 10 (see Figure 12). of CFVC is most easily determined empirically. In general,
large values minimize the chance of exceeding BVCEX,
2. Programmable Frequency Ramping: H frequency
but generate long PLL capture times.
transitions from high to low present a special problem for
deflection output stages without current limiting. If, dur- 3. Phase Voltage Range vs Delay Time: The recom-
ing such a transition, the output transistor on-time in- mended phase voltage range to use on pin 10 (PHASE)
creases excessively before the B+ voltage has de- depends on the delay time of the deflection output stage.
creased to its final level, then the deflection inductor Delay time is defined as the time from the rising edge of
current ramps too high and the induced flyback pulse H Drive to the center of flyback. For best performance
can exceed the breakdown voltage, BVCEX, of the output the phase voltage range should be in the unshaded area
transistor. To prevent this, the rate of change of the VCO of Figure 11.
frequency must be limited.
Recommended Phase Voltage for 640 x 480 @ 60 Hz
DS012917-11
FIGURE 11.
7 www.national.com
Typical Application
DS012917-12
*Actual value depends on the application and the ambient noise level inside the monitor.
FIGURE 12.
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number LM1290N
NS Package Number N14A
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LM1290 Autosync Horizontal Deflection Processor [ Pobierz całość w formacie PDF ]